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R5F5671CDDFM bảng dữ liệu(PDF) 152 Page - Renesas Technology Corp

tên linh kiện R5F5671CDDFM
Giải thích chi tiết về linh kiện  120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark, up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM, various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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R01DS0373EJ0110 Rev.1.10
Page 152 of 178
Apr 15, 2022
RX671 Group
2. Electrical Characteristics
2.4.7.17
SDHI
Note 1. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in
combination with the pins in the same group. All SDHI AC timings are measured in combination with the pins in the same group.
Figure 2.88
SD Host Interface Input/Output Signal Timing
Table 2.50
SDHI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
Symbol
Min.
Max.
Unit
Test Conditions*1
SDHI
SDHI_CLK pin output cycle time
tPP(SD)
20
—
ns
Figure 2.88
SDHI_CLK pin output high pulse width
tWH(SD)
0.4 × tPP(SD)
—ns
SDHI_CLK pin output low pulse width
tWL(SD)
0.4 × tPP(SD)
—ns
SDHI_CLK pin output rise time
tTLH(SD)
—3
ns
SDHI_CLK pin output fall time
tTHL(SD)
—3
ns
Output data delay time (data transfer mode) for
SDHI_CMD and SDHI_D0 to SDHI_D3 pins
tODLY(SD)
–6.5
4
ns
Input data setup time for SDHI_CMD and SDHI_D0 to
SDHI_D3 pins
tISU(SD)
6—
ns
Input data hold time for SDHI_CMD and SDHI_D0 to
SDHI_D3 pins
tIH(SD)
2—
ns
SDHI_CLK output
SDHI_CMD, SDHI_D3 to SDHI_D0 input
SDHI_CMD, SDHI_D3 to SDHI_D0 output
tWL(SD)
tWH(SD)
tPP(SD)
tISU(SD) tIH(SD)
tTLH(SD)
tTHL(SD)
tODLY(SD)
tODLY(SD)
VIH
VIL
VIL
VIL
VIH
VIH
50% VCC
50% VCC



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