R5F5671CDDFM datasheet(129/178 Pages) RENESAS

tên linh kiện	R5F5671CDDFM

Giải thích chi tiết về linh kiện	120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark, up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM, various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,

PDF	178 Pages

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nhà sản xuất	RENESAS [Renesas Technology Corp]

Trang chủ	http://www.renesas.com

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129 / 178 page

R01DS0373EJ0110 Rev.1.10

Page 129 of 178

Apr 15, 2022

RX671 Group

2. Electrical Characteristics

2.4.7.10

RSCI

Note 1. tPAcyc: PCLKA cycle; tScyc: SCK cycle

Figure 2.55

SCK Clock Input Timing

Figure 2.56

RSCI Input/Output Timing: Clock Synchronous Mode

Table 2.39

RSCI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-speed interface high-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

RSCI

Input clock cycle

Asynchronous

tScyc

—

tPAcyc

Figure 2.55

Clock synchronous

—

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

—5

Input clock fall time

tSCKf

—5

Output clock cycle

Asynchronous

tScyc

6—

tPAcyc

Clock synchronous

—

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

tSCKr

—5

Output clock fall time

tSCKf

—5

Receive data setup time

Master

tRXS

0.5

—

Figure 2.56

Slave

2.5

—

Receive data hold time

Master

tRXH

—

Slave

2.5

—

Transmit data delay time

Master

tTXD

—4

Slave

—

tSCKW

tSCKr

tSCKf

tScyc

SCKn

(n = 010, 011)

tTXD

tRXS tRXH

TXDn

RXDn

SCKn

(n = 010, 011)

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