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R5F5671CDDFM bảng dữ liệu(PDF) 123 Page - Renesas Technology Corp |
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R5F5671CDDFM bảng dữ liệu(HTML) 123 Page - Renesas Technology Corp |
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123 / 178 page  R01DS0373EJ0110 Rev.1.10 Page 123 of 178 Apr 15, 2022 RX671 Group 2. Electrical Characteristics 2.4.7.9 SCI Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle Table 2.36 SCIk, SCIh, and SCIm Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the drive capacity control register. Item Symbol Min. Max. Unit*1 Test Conditions SCIk, SCIh Input clock cycle Asynchronous tScyc 4 — tPBcyc Figure 2.47 Clock synchronous 6— Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous (SCIk) tScyc 6— tPBcyc Asynchronous (SCIh) 8— Clock synchronous 4— Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Clock synchronous tTXD — 28 ns Figure 2.48 Receive data setup time Clock synchronous tRXS 15 — ns Receive data hold time Clock synchronous tRXH 5— ns SCIm Input clock cycle Asynchronous tScyc 4— tPAcyc Figure 2.47 Clock synchronous 6— Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous tScyc 6— tPAcyc Clock synchronous 4— Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Master tTXD — 15 ns Figure 2.48 Slave — 28 Receive data setup time Clock synchronous tRXS 20 — ns Receive data hold time Clock synchronous tRXH 5— ns |
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