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ADE7932 bảng dữ liệu(PDF) 115 Page - Analog Devices

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Data Sheet
ADE7978/ADE7933/ADE7932/ADE7923
Rev. D | Page 115 of 125
Table 48. MASK1 Register (Address 0xE50B)
Bits
Bit Name
Default Value
Description
0
NLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters the no load
condition based on the total active and reactive powers.
1
FNLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters the no load
condition based on the fundamental active and reactive powers.
2
VANLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters the no load
condition based on the apparent power.
3
ZXTOVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A
voltage is missing.
4
ZXTOVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase B
voltage is missing.
5
ZXTOVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase C
voltage is missing.
6
ZXTOIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase A
current is missing.
7
ZXTOIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase B
current is missing.
8
ZXTOIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on the Phase C
current is missing.
9
ZXVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase A voltage.
10
ZXVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase B voltage.
11
ZXVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase C voltage.
12
ZXIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase A current.
13
ZXIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase B current.
14
ZXIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on the
Phase C current.
15
RSTDONE
0
Because the RSTDONE interrupt cannot be disabled, this bit has no function. It can be set
to 1 or cleared to 0 with no effect on the device.
16
Sag
0
When this bit is set to 1, it enables an interrupt when a sag event occurs on the phase
indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 49).
17
OI
0
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on the
phase indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 49).
18
OV
0
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on the
phase indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 49).
19
SEQERR
0
When this bit is set to 1, it enables an interrupt when a negative to positive zero crossing
on the Phase A voltage is followed by a negative to positive zero crossing on the Phase C
voltage instead of on the Phase B voltage.
20
MISMTCH
0
When this bit is set to 1, it enables an interrupt when ||ISUM| − |INWV|| > |ISUMLVL|, where
ISUMLVL is the value of the ISUMLVL register (Address 0x4398). For more information, see
the Neutral Current Mismatch section.
[22:21]
Reserved
00
Reserved. These bits do not manage any functionality.
23
PKI
0
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the current channel has ended.
24
PKV
0
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the voltage channel has ended.
25
CRC
0
When this bit is set to 1, it enables an interrupt when the latest checksum value is different
from the checksum value computed when the run register was set to 1.
[31:26]
Reserved
00 0000
Reserved. These bits do not manage any functionality.



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