DATA SHEET

HVC 4x Family

TDK-Micronas GmbH

July 9, 2021; DSH000216_001EN

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1.1. Features

The following list gives an overview of the features of the HVC 4x family (see Table 1–2

on page 11 for a detailed feature list).

Core and Interrupt System

(Memory Protection Unit MPU for the 64 KB version)

– Nested Vectored Interrupt Controller (NVIC):

over 20 interrupt lines, each programmable with 8 (3-bit) priority levels.

– 24-bit SysTick timer

– CPU operating modes: ACTIVE, OVERVOLTAGE

– Power-saving modes (CPU inactive): IDLE, SLEEP

– Retention mode for start-stop applications: RETENTION

– Programmable CPU clock of up to 20 MHz

Internal Oscillators:

– Main oscillator: 40 MHz with clock divider and EMI reduction

– Auxiliary oscillator: 35 kHz

Memory

– RAM: 2/4 KB

– Flash: 32/64 KB

– NVRAM: 512 byte (448 byte for customer use)

– For the HVC 4x family there is additional information available how to use the diag-

nostic and safety features of the IC on top of the standard AEC-Q100 requirements.

This functional safety readiness results in additional documentation like FMEDA sum-

mary report and a dedicated Functional Safety Manual.

– The Functional Safety Manual describes, how to implement the Application Software

and Application itself in order to correctly and beneficially utilize the regarding device

features. The Functional Safety Manual provides information to support customers to

realize an ISO 26262 compliant system using the HVC 4x family as a QM hardware

part inside functional safety applications.

– The FMEDA summary report describes the assumed Safety Goal, the corresponding

Failure Modes as well as the base failure rates according to IEC TR 62380.