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32G474 bảng dữ liệu(PDF) 199 Page - STMicroelectronics

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STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
201
5.3.29
QUADSPI characteristics
Unless otherwise specified, the parameters given in Table 108 and Table 109 for Quad SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 17: General operating conditions, with the
following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C = 15 or 20 pF
•
Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 108. Quad SPI characteristics in SDR mode(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
F(QCK)
Quad SPI clock
frequency
1.71 < VDD< 3.6 V,
CLOAD = 15 pF
Voltage Range 1
--
50
MHz
1.71 < VDD< 3.6 V,
CLOAD = 20 pF
Voltage Range 2
--
110
tw(CKH) Quad SPI clock high
and low time
Even division
PRESCALER [7:0]
n =0,1, 3, 5 ...
t(CK)/2-0.5
-
t(CK)/2+1
ns
tw(CKL)
t(CK)/2-1
-
t(CK)/2+0.5
tw(CKH) Quad SPI clock high
and low time
Odd division
PRESCALER [7:0]
n =2,4, 6, 8...
(n/2)*t(CK)/(n+1) - 0.5
-
(n/2)*t(CK)/(n+1) + 1
tw(CKL)
(n/2+1)*t(CK)/(n+1) - 1
-
(n/2+1)*t(CK)/(n+1) +0.5
ts(IN)
Data input setup time 1.71 < VDD< 3.6 V
1
-
-
th(IN)
Data input hold time
1.71 < VDD< 3.6 V
5
-
-
tv(OUT)
Data output valid
time
1.71 < VDD< 3.6 V
-
1
1.5
th(OUT) Data output hold time 1.71 < VDD< 3.6 V
0.5
-
-
1. Guaranteed by characterization results.
Table 109. QUADSPI characteristics in DDR mode(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
F(QCK)
Quad SPI clock
frequency
1.71 < VDD< 3.6 V,
CLOAD = 15 pF
Voltage Range 1
--
50
MHz
1.71 < VDD< 3.6 V,
CLOAD = 20 pF
Voltage Range 2
--
70



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