ADIN1110BCPZ-R7 datasheet(101/104 Pages) AD

101 / 104 page

Data Sheet

ADIN1110

REGISTERS

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Rev. 0 | 101 of 104

Frame Generator Frame Length Register

Device Address: 0x1F; Register Address: 0x8025, Reset: 0x006B, Name: FG_FRM_LEN

This register specifies the data field frame length in bytes. In addition to the data field, six bytes are added for the source address, six bytes

for the destination address, two bytes for the length field, and four bytes for the frame check sequence (FCS). The total length is the data field

length plus 18.

Table 210. Bit Descriptions for FG_FRM_LEN

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_FRM_LEN

The Data Field Frame Length in Bytes.

0x6B

R/W

Frame Generator Interframe Gap Length Register

Device Address: 0x1F; Register Address: 0x8026, Reset: 0x000C, Name: FG_IFG_LEN

This register specifies the length in bytes of the interframe gap to be inserted between frames by the frame generator.

Table 211. Bit Descriptions for FG_IFG_LEN

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_IFG_LEN

Frame Generator Interframe Gap Length. This register specifies the length in bytes of the interframe gap to

be inserted between frames by the frame generator.

0xC

R/W

Frame Generator Number of Frames High Register

Device Address: 0x1F; Register Address: 0x8027, Reset: 0x0000, Name: FG_NFRM_H

This register is Bits[31:16] of a 32-bit register that specifies the number of frames to be generated each time the frame generator is enabled or

restarted.

Table 212. Bit Descriptions for FG_NFRM_H

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_NFRM_H

Bits[31:16] of the Number of Frames to be Generated.

0x0

R/W

Frame Generator Number of Frames Low Register

Device Address: 0x1F; Register Address: 0x8028, Reset: 0x0100, Name: FG_NFRM_L

This register is Bits[15:0] of a 32-bit register that specifies the number of frames to be generated each time the frame generator is enabled or

restarted.

Table 213. Bit Descriptions for FG_NFRM_L

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_NFRM_L

Bits[15:0] of the Number of Frames to be Generated.

0x100

R/W

Frame Generator Done Register

Device Address: 0x1F; Register Address: 0x8029, Reset: 0x0000, Name: FG_DONE

This register is used to indicate that the frame generator has completed the generation of the number of frames requested in the FG_NFRM_H

and FG_NFRM_L registers.

Table 214. Bit Descriptions for FG_DONE

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

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