DS31256 datasheet(147/183 Pages) MAXIM

147 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

147 of 183

11.

LOCAL BUS

11.1 General Description

The local bus can operate in two modes, either as a PCI bridge (master mode) or as a configuration bus

(slave mode). This selection is made in hardware by connecting the LMS pin high or low. Figure 11-1

shows an example of the local bus operating in the PCI bridge mode. In this example, the host can access

the control ports on the T1/E1 devices through the local bus. Figure 11-2 also shows an example of the

PCI bridge mode, but the local bus arbitration is enabled, which allows a local CPU to control when the

host can have access to the local bus. To access the local bus, the host must first request the bus and then

wait until it is granted. Figure 11-3 features an example of the configuration mode. In this mode, the

CPU on the local bus configures and monitors the DS31256. In this mode, the host on the PCI/custom

bus cannot access the DS31256 and the PCI/custom bus is only used to transfer HDLC packet data to

and from the host.

Table 11-A lists all the local bus pins and their applications in both operating modes. The local bus

operates only in a nonmultiplexed fashion; it is not capable of operating as a multiplexed bus. For both

operating modes, the local bus can be set up for either Intel or Motorola type buses. This selection is

made in hardware by connecting the LIM pin high or low.

Table 11-A. Local Bus Signals

SIGNAL

FUNCTION

PCI BRIDGE

MODE (LMS = 0)

CONFIGURATION MODE

(LMS = 1)

LD[0:15]

Data Bus

Input on Read/Output on Write

Input on Write/Output on Read

LA[0:19]

Address Bus

Output

Input

LWR (LR/W)

Bus Write (Read/Write Select)

Output

Input

LRD (LDS)

Bus Read (Data Strobe)

Output

Input

LBHE

Byte High Enable

Output

Tri-stated

LIM

Intel/Motorola Select

Input

LINT

Interrupt

Input

Output

LMS

Mode Select

Input

LCLK

Bus Clock

Output

Tri-stated

LRDY

Bus Ready

Input

Ignored

LCS

Chip Select

Ignored

Input

LHOLD (

LBR)

Hold Request (Bus Request)

Output

Tri-stated

LHLDA (

LBG)

Hold Acknowledge (Bus Grant)

Input

Ignored

LBGACK

Bus Acknowledge

Output

Tri-stated

Note: Signals shown in parentheses are active when Motorola mode (LIM = 1) is selected.

DS31256 bảng dữ liệu(PDF) 147 Page - Maxim Integrated Products

DS31256 bảng dữ liệu(HTML) 147 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL