DS31256_V01 datasheet(143/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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10.2.3 Command Bits (PCMD1)

Bit 0/I/O Space Control (IOC). This read-only bit is forced to 0 by the device to indicate that it does not respond

to I/O space accesses.

Bit 1/Memory Space Control (MSC). This read/write bit controls whether or not the device responds to accesses

by the PCI bus to the memory space, which is the local bus. When this bit is set to 0, the device ignores accesses

attempted to the local bus. When set to 1, the device allows accesses to the local bus. This bit should be set to 0

when the local bus operates in configuration mode. This bit is forced to 0 when a hardware reset is initiated

through the

PRST pin.

0 = ignore accesses to the local bus

1 = allow accesses to the bus

Bit 2/Master Control (MASC). This read-only bit is forced to 0 by the device since it cannot act as a bus master.

Bit 3/Special Cycle Control (SCC). This read-only bit is forced to 0 by the device to indicate that it cannot

decode special cycle operations.

Bit 4/Memory Write and Invalidate Command Enable (MWEN). This read-only bit is forced to 0 by the

device to indicate that it cannot generate the memory write and invalidate command.

Bit 5/VGA Control (VGA). This read-only bit is forced to 0 by the device to indicate that it is not a VGA-

compatible device.

Bit 6/Parity Error Response Control (PARC). This read/write bit controls whether or not the device should

ignore parity errors. When this bit is set to 0, the device ignores any parity errors that it detects and continues to

operate normally. When this bit is set to 1, the device must act on parity errors. This bit is forced to 0 when a

hardware reset is initiated through the

PRST pin.

0 = ignore parity errors

1 = act on parity errors

Bit 7/Address Stepping Control (STEPC). This read-only bit is forced to 0 by the device to indicate that it is not

capable of address/data stepping.

Bit 8/PCI System Error Control (PSEC). This read/write bit controls whether or not the device should enable

the

PSERR output pin. When this bit is set to 0, the device disables the PSERR pin. When this bit is set to 1, the

device enables the

PSERR pin. This bit is forced to 0 when a hardware reset is initiated through the PRST pin.

0 = disable the

PSERR pin

1 = enable the

PSERR pin

Bit 9/Fast Back-to-Back Master Enable (FBBEN). This read-only bit is forced to 0 by the device to indicate that

it is not capable of generating fast back-to-back transactions to different agents.

Bits 10 to 15/Reserved. These read-only bits are forced to 0 by the device.

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