DS31256_V01 datasheet(113/183 Pages) MAXIM

113 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

113 of 183

descriptor pointer and PV fields in the packet descriptor to 0 to ready them for transmission). The second

option allows the software a cleaner error-recovery technique. See Figure 9-14 for more details.

Figure 9-14. Transmit DMA Error Recovery Algorithm

Host Actions

The host typically handles the transmit DMA as follows:

1) The host places readied packets into the pending queue.

2) The host either polls (or is interrupted) that some outgoing packets have completed transmission and

that it should read the done queue.

3) If done queue reports that an error was incurred and that a packet was not transmitted, the host must

requeue the packet for transmission.

Transmit DMA Actions

A typical scenario for the transmit DMA is as follows:

1) The transmit DMA constantly reads the pending queue looking for packets that are queued for

transmission.

2) The transmit DMA updates the done queue as packets or data buffers to complete transmission.

3) If an error occurs, the transmit DMA disables the channel and waits for the host to request that the

channel be enabled.

Read Done Queue

Status = 1xx?

Data Buffers and

Packet Descriptor

Space Available

for Reuse

Yes

Set CHRST = 1 for

the Next Descriptor

Written to the

Pending Queue

Set the PV and the Next

Pending Descriptor Pointer

Fields to 0 in the Errored

Packet Descriptor

Place the Errored Packet

Descriptor Back into the

Pending Queue for

Retransmission

DS31256 bảng dữ liệu(PDF) 113 Page - Maxim Integrated Products