PCIMX6QP7AVT2AB datasheet(107/160 Pages) NXP

tên linh kiện	PCIMX6QP7AVT2AB

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Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

107

4.12.12.2 D-PHY Signaling Levels

The signal levels are different for differential HS mode and single-ended LP mode. Figure 64 shows both

the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below

the LP low-level input threshold such that LP receiver always detects low on HS signals.

Figure 64. D-PHY Signaling Levels

LP Line Receiver DC Specifications

VIL

Input low voltage

—

550

VIH

Input high voltage

—

920

—

VHYST

Input hysteresis

—

Contention Line Receiver DC Specifications

VILF

Input low fault threshold

—

200

—

450

Table 64. Electrical and Timing Information (continued)

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

HS Vout

Range

HS Vcm

Range

Max VOD

Min VOD

VCMTX,MIN

VOLHS

VCMTX,MAX

VOHHS

LP VIL

VOL

VIH

VOH,MAX

VOH,MIN

VIH

VIL

LP Threshold

Region

VGNDSH,MA

VGNDSH,MIN

GND

LP VOL

HS Differential Signaling

LP Single-ended Signaling

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