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127 / 166 page  Electrical Characteristics i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018 NXP Semiconductors 127 NOTE • All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal AUDx_TXC/AUDx_RXC and/or the frame sync AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures. • All timings are on Audiomux Pads when SSI is being used for data transfer. • The terms, WL and BL, refer to Word Length(WL) and Bit Length(BL). • For internal Frame Sync operation using external clock, the frame sync timing is the same as that of transmit data (for example, during AC97 mode of operation). Table 82. SSI Transmitter Timing with Internal Clock ID Parameter Min Max Unit Internal Clock Operation SS1 AUDx_TXC/AUDx_RXC clock period 81.4 — ns SS2 AUDx_TXC/AUDx_RXC clock high period 36.0 — ns SS4 AUDx_TXC/AUDx_RXC clock low period 36.0 — ns SS6 AUDx_TXC high to AUDx_TXFS (bl) high — 15.0 ns SS8 AUDx_TXC high to AUDx_TXFS (bl) low — 15.0 ns SS10 AUDx_TXC high to AUDx_TXFS (wl) high — 15.0 ns SS12 AUDx_TXC high to AUDx_TXFS (wl) low — 15.0 ns SS14 AUDx_TXC/AUDx_RXC Internal AUDx_TXFS rise time — 6.0 ns SS15 AUDx_TXC/AUDx_RXC Internal AUDx_TXFS fall time — 6.0 ns SS16 AUDx_TXC high to AUDx_TXD valid from high impedance — 15.0 ns SS17 AUDx_TXC high to AUDx_TXD high/low — 15.0 ns SS18 AUDx_TXC high to AUDx_TXD high impedance — 15.0 ns Synchronous Internal Clock Operation SS42 AUDx_RXD setup before AUDx_TXC falling 10.0 — ns SS43 AUDx_RXD hold after AUDx_TXC falling 0.0 — ns |
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