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STM32WL55JC bảng dữ liệu(PDF) 135 Page - STMicroelectronics

tên linh kiện STM32WL55JC
Giải thích chi tiết về linh kiện  Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0 LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32WL55JC bảng dữ liệu(HTML) 135 Page - STMicroelectronics

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DS13293 Rev 1
135/145
STM32WL55/54xx
Electrical characteristics
135
JTAG/SWD characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 25: General operating conditions, with the following configuration:
•
capacitive load C = 30 pF
•
measurement done at CMOS levels: 0.5 x VDD.
Refer to Section 5.3.16: I/O port characteristics for more details.
Table 96. Dynamic JTAG characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
1/tc(TCK)
TCK clock frequency
2.7 V < VDD < 3.6 V
-
-
33
MHz
1.8 V < VDD < 3.6 V
-
-
25
tisu(TMS)
TMS input setup time
-
0.5
-
-
ns
tih(TMS)
TMS input hold time
-
1
-
-
tisu(TDI)
TDI input setup time
-
1
-
-
tih(TDI)
TDI input hold time
-
2.5
-
-
tov(TDO)
TDO output valid time
2.7 V < VDD < 3.6 V
-
12
15
1.8 V< VDD < 3.6 V
-
12
20
toh(TDO)
TDO output hold time
-
10
-
-
Table 97. Dynamic SWD characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
1/tc(SWCLK)
SWCLK clock frequency
2.7 V < VDD < 3.6 V
-
-
58
MHz
1.8 < VDD < 3.6 V
-
-
41
tisu(SWDIO) SWDIO input setup time
-
1
-
-
ns
tih(SWDIO) SWDIO input hold time
-
2
-
-
tov(SWDIO) SWDIO output valid time
2.7 V < VDD < 3.6 V
-
15
17
1.8 V < VDD < 3.6 V
-
15
24
toh(SWDIO) SWDIO output hold time
-
9
-
-



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