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STM32L552VCU6QXXX bảng dữ liệu(PDF) 237 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS
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STM32L552VCU6QXXX bảng dữ liệu(HTML) 237 Page - STMicroelectronics

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STM32L552xx
Electrical characteristics
307
Figure 42. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 106: NRST pin characteristics. Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.17
Extended interrupt and event controller input (EXTI) characteristics
The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 106. NRST pin characteristics(1)
1.
Guaranteed by design.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST input low level
voltage
--
-
0.3ₓVDDIOx
V
VIH(NRST)
NRST input high level
voltage
-0.7ₓVDDIOx
--
Vhys(NRST)
NRST Schmitt trigger
voltage hysteresis
--
200
-
mV
RPU
Weak pull-up equivalent
resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order)
.
VIN = VSS
25
40
55
kΩ
VF(NRST)
NRST input filtered
pulse
--
-
70
ns
VNF(NRST)
NRST input not filtered
pulse
1.71 V ≤ VDD
≤ 3.6 V
350
-
-
ns
MS19878V3
RPU
VDD
Internal reset
External
reset circuit
(1)
NRST
(2)
Filter
0.1 μF
Table 107. EXTI input characteristics(1)
1. Guaranteed by design.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PLEC
Pulse length to event
controller
-20
-
-
ns



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