ST7LITE39 datasheet(151/167 Pages) STMICROELECTRONICS

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ST7LITE3

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13.10 COMMUNICATION INTERFACE CHARACTERISTICS

13.10.1 SPI - Serial Peripheral Interface

Subject to general operating conditions for VDD,

fOSC, and TA unless otherwise specified.

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(SS, SCK, MOSI, MISO).

Figure 98. SPI Slave Timing Diagram with CPHA=0 3)

Notes:

1. Data based on design simulation and/or characterisation results, not tested in production.

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK =

1/tc(SCK)

SPI clock frequency

Master

fCPU=8MHz

fCPU/128 =

0.0625

fCPU/4 =

MHz

Slave

fCPU=8MHz

fCPU/2 =

tr(SCK)

tf(SCK)

SPI clock rise and fall time

see I/O port pin description

tsu(SS)

SS setup time

Slave

120

th(SS)

SS hold time

Slave

120

tw(SCKH)

tw(SCKL)

SCK high and low time

Master

Slave

100

tsu(MI)

tsu(SI)

Data input setup time

Master

Slave

100

th(MI)

th(SI)

Data input hold time

Master

Slave

100

ta(SO)

Data output access time

Slave

120

tdis(SO)

Data output disable time

Slave

240

tv(SO)

Data output valid time

Slave (after enable edge)

120

th(SO)

Data output hold time

tv(MO)

Data output valid time

Master (before capture

edge)

0.25

tCPU

th(MO)

Data output hold time

0.25

SS INPUT

CPHA=0

MOSI INPUT

MISO OUTPUT

CPHA=0

tc(SCK)

tw(SCKH)

tw(SCKL)

tr(SCK)

tf(SCK)

tv(SO)

ta(SO)

tsu(SI)

th(SI)

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

seenote2

CPOL=0

CPOL=1

tsu(SS)

th(SS)

tdis(SO)

th(SO)

see

note 2

BIT1 IN

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