VSC7440 datasheet(415/444 Pages) MICROSEMI

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Electrical Specifications

VMDS-10492 VSC7440 Datasheet Revision 4.2

398

Figure 149 •

Two-Wire Serial Write Timing Diagram

The following table lists the AC specifications for the serial interface. Standard mode is defined as

100 kHz and fast mode is 400 kHz. The data in this table assumes that the software-configurable two-

wire interface timing parameters, SS_SCL_HCNT, SS_SCL_LCNT, FS_SCL_HCNT, and

FS_SCL_LCNT, are set to valid values for the selected speed.

Table 317 •

Two-Wire Serial Interface AC Specifications

Standard Mode

Fast Mode

Parameter

Symbol Minimum

Maximum

Minimum

Maximum

Unit Condition

TWI_SCL clock frequency

100

400

kHz

TWI_SCL low period

tLOW

4.7

1.3

µs

TWI_SCL high period

tHIGH

4.0

0.6

µs

TWI_SCL and TWI_SDA

rise time

1000

300

TWI_SCL and TWI_SDA

fall time

300

TWI_SDA setup time to

TWI_SCL fall

tSU_DAT 250

100

300

TWI_SDA hold time to

TWI_SCL fall1

An external device must provide a hold time of at least 300 ns for the TWI_SDA signal to bridge the undefined region of the falling

edge of the TWI_SCL signal.

tHD_DAT 300

3450

300

900

300 ns delay

enabled in

ICPU_CFG::TWI_

CONFIG register.

Setup time for repeated

START condition

tSU_STA

4.7

0.6

µs

Hold time after repeated

START condition

tHD_STA 4.0

0.6

µs

Bus free time between

STOP and START

conditions

tBUF

4.7

1.3

µs

Clock to valid data out2

Some external devices may require more data in hold time (target device’s tHD_DAT) than what is provided by tVD_DAT, for example,

300 ns to 900 ns. The minimum value of tVD_DAT is adjustable; the value given represents the recommended minimum value,

which is enabled in ICPU_CFG::TWI_CONFIG.TWI_DELAY_ENABLE.

tVD_DAT 300

300

Pulse width of spike

suppressed by input filter

on TWI_SCL or TWI_SDA

tVD_DAT

TWI_SDA

TWI_SCL

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