VSC7440 datasheet(407/444 Pages) MICROSEMI

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Electrical Specifications

VMDS-10492 VSC7440 Datasheet Revision 4.2

390

6.2.8

Serial Interface (SI) Boot Master Mode

The following table lists the timing specifications for SI boot master mode.

6.2.9

Serial Interface (SI) Master Mode

All serial interface (SI) timing requirements for master mode are specified relative to the input low and

input high threshold levels. The following illustration shows the timing parameters and measurement

points.

Figure 137 •

SI Timing Diagram for Master Mode

All SI signals comply with the specifications shown in the following table. The SI input timing

requirements are requested at the pins of the device.

Table 309 •

SI Boot Timing Specifications for Master Mode

Parameter

Symbol Minimum Maximum

Unit Condition

Clock frequency

251

Frequency is programmable. The startup frequency is 8.1 MHz.

MHz

Clock cycle time

Clock time high

tW(CH)

Clock time low

tW(CL)

Clock rise time and fall time

tR, tF

Between VIL(MAX) and

VIH(MIN). CL=30 pF.

SI_DO setup time to clock

tSU(DO)

SI_DO hold time from clock

tH(DO)

Enable active before first clock tLEAD

Enable inactive after clock

tLAG

5ns

SI_DI setup time to clock

tSU(DI)

SI_DI hold time from clock

tH(DI)

–2

Table 310 •

SI Timing Specifications for Master Mode

Parameter

Symbol Minimum Maximum

Unit Condition

Clock frequency

251

MHz

Clock cycle time

Clock time high

tW(CH)

Clock time low

tW(CL)

SI_nCS0

(output)

tLEAD

tW(CH)

tSU(DO)

tH(DO)

tSU(DI)

tH(DI)

tLAG

tW(CL)

SI_CLK

(output)

SI_DO

(output)

SI_DI

(input)

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