VSC7440 datasheet(337/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

320

Disable automatic link training for PICe endpoint.

PCIE_CFG.LTSSM_DIS = 1. Configure and enable PCIe SERDES for 2G5 mode.

SERDES6G_MISC_CFG = 0x00000031.

SERDES6G_OB_CFG = 0x60000171.

SERDES6G_OB_CFG1 = 0x000000B0.

SERDES6G_DES_CFG = 0x000068A6.

SERDES6G_IB_CFG = 0x3D57AC37.

SERDES6G_IB_CFG1 = 0x00110FF0.

SERDES6G_COMMON_CFG = 0x00024009.

MCB_SERDES6G_ADDR_CFG = 0x80000004 and wait until bit 31 is cleared.

SERDES6G_PLL_CFG = 0x00030F20.

10. MCB_SERDES6G_ADDR_CFG = 0x80000004 and wait until bit 31 is cleared.

11. Wait at least 20 ms.

12. SERDES6G_IB_CFG = 0x3D57AC3F.

13. SERDES6G_MISC_CFG = 0x00000030.

14. MCB_SERDES6G_ADDR_CFG = 0x80000004 and wait until bit 31 is cleared.

15. Wait at least 60 ms.

16. SERDES6G_IB_CFG = 0x3D57ACBF.

17. SERDES6G_IB_CFG1 = 0x00103FF0.

18. MCB_SERDES6G_ADDR_CFG = 0x80000004 and wait until bit 31 is cleared.

To optionally disable BAR1:

PCIE_CFG.PCIE_BAR_WR_ENA = 1

BAR1 = 0x00000000

PCIE_CFG.PCIE_BAR_WR_ENA = 0

To optionally increase BAR2 from 128 to 256 megabytes:

PCIE_CFG.PCIE_BAR_WR_ENA = 1

BAR2 = 0x0FFFFFFF

PCIE_CFG.PCIE_BAR_WR_ENA = 0

To optionally change selected PCIe configuration space values:

•

Write Vendor ID/Device ID using DEVICE_ID_VENDOR_ID.

•

Write Class Code/Revision ID using CLASS_CODE_REVISION_ID.

•

Write Subsystem ID/Subsystem Vendor ID using SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID.

Enable automatic link training for PCIe endpoint

PCIE_CFG.LTSSM_DIS = 0

The last step enables the endpoint for link training, and the root complex will then be able to initialize the

PCIe endpoint. After this the PCIE parameters must not be changed anymore.

HSIO::SERDES6G_IB_CFG1

SERDES configuration

HSIO::SERDES6G_OB_CFG

SERDES configuration

HSIO::SERDES6G_OB_CFG1

SERDES configuration

HSIO::SERDES6G_DES_CFG

SERDES configuration

HSIO::SERDES6G_PLL_CFG

SERDES configuration

HSIO::SERDES6G_MISC_CFG

SERDES configuration

HSIO::MCB_SERDES6G_ADDR_CFG

SERDES configuration

PCIE::DEVICE_ID_VENDOR_ID,

PCIE::CLASS_CODE_REVISION_ID,

PCIE::SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID

Device parameter customization

PCIE::BAR1, PCIE::BAR2

Base address register customization

Table 236 •

Manual PCIe Bring-Up Registers (continued)

Description

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