VSC7440 datasheet(245/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

228

Configuring costs is done indirectly by setting the HSCH_CFG_CFG.DWRR_IDX first (pointing to the

scheduler element to configure), after which the costs are accessible through the HSCH_DWRR

registers.

The following table lists the registers associated with the arbitration algorithm.

3.24.7.5 Queue Shapers

In addition to the shaping capabilities at the output of each scheduling element, it is also possible to

shape individual queues. These shapers are single leaky bucket based. The devices contain 832 such

shapers that can be assigned to any of the 3,328 queues. The assignment of queue shapers is done

through the HSCH::QSHP_ALLOC_CFG register. This is replicated per scheduling elements in layer 0,

and defines the range of inputs on the element that should have queue shapers assigned, and the index

of the first of the 832 shapers to allocate to it. The shapers must be linked together for the leaking

process in HSCH::QSHP_CONNECT

For example, to configure queue shapers on inputs 5 to 7 on elements 100 to 120, use the queue

shapers from 400 to 462.

For I in 100 to 120 loop

HSCH:QSHP_ALLOC_CFG[I]:QSHP_ALLOC_CFG.QSHP_MIN := 5

HSCH:QSHP_ALLOC_CFG[I]:QSHP_ALLOC_CFG.QSHP_MAX := 7

HSCH:QSHP_ALLOC_CFG[I]:QSHP_ALLOC_CFG.QSHP_BASE := 3*(I-100)+400

HSCH:QSHP_ALLOC_CFG[I]:QSHP_CONNECT.SE_LEAK_LINK := I+1;

Endloop

(terminate chain)

HSCH:QSHP_ALLOC_CFG[120]:QSHP_CONNECT.SE_LEAK_LINK := 120

The leak process operates as for the SE shapers and must be configured in

HSCH:HSCH_LEAK_LISTS[3].

The indexes of shapers allocated to a set of queues are only used in the QSHP_BASE settings. The

shapers are accessed afterwards through the QSHP_CFG and QSHP_STATUS registers, accessed

indirectly after setting HSCH_CFG_CFG.CFG_SE_IDX to the desired scheduling element.

For example, to configure the shaper on input 6 of element 118 to shape to 1.2 Mbps, set

HSCH::HSCH_CFG_CFG.CFG_SE_IDX := 118 and HSCH:QSHP_CFG[6].QSHP_CIR_CFG.CIR_RATE

:= 12 (assuming the leak chain is configured for unit 100 kbps).

3.24.7.6 Miscellaneous Scheduler Features

The following table lists some features that might be useful.

Table 154 •

Scheduler Arbitration Registers Overview

Description

HSCH::SE_CFG

Selects arbitration mode (data/line/frame) and number of inputs running DWRR

HSCH::CFG_CFG

Selects for which element to configure/monitor DWRR algorithm

HSCH::DWRR_ENTRY Configures costs for each input

HSCH::INP_STATE

Returns input states for a scheduler element

Table 155 •

Miscellaneous Scheduler Registers Overview

Field

Description

SE_CONNECT_VLD

Stops the whole scheduler operation. Can be useful when reconfiguring the hierarchy.

LEAK_DIS

Disables leaking process.

FRM_ADJ

Sets the byte difference between line and data rate calculations.

DEQUEUE_DIS

Disables transmissions per port.

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