AM79C930VCW datasheet(132/161 Pages) AMD

132 / 161 page

AMD

P R E L I M I N A R Y

132

Am79C930

PCMCIA MEMORY WRITE ACCESS

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

tAVWL

Address setup to

↓

tAVWH

Address setup to

↑

100

tWMAX

Write recovery time

(Address hold from

↑ )20

tELWH

CE setup to WE

↑

140

tELWL

CE setup to WE

↓

0ns

tGHEH

CE hold from OE

↑ (READ) or CE

hold from

↑ (WRITE)

tGHWL

OE setup to WE

↓

tWHGL

OE hold from WE

↑

tWLWH

WE pulse width

120

tWLWTV

WAIT valid from WE

↓

tWTLWTH

WAIT pulse width

Notes 1, 2

53 X TCLKIN

tWTHWH

WE hold from WAIT

↑

0ns

tDVWH

Data setup to

↑

tWMDX

Data hold from

↑

tGHQZ

Data disabled from

↑

Note 2

tWLQZ

Data disabled from

↓

Note 2

tWHQNZ

Data enabled from

↑

Note 2

tGLQNZ

Data enabled from

↓

Note 2

Notes:

1. The max value for this parameter assumes the following worst case situation:

Value

Worst Case

FLASH and SRAM wait states set at “3.”

Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins

instruction fetch cycle to FLASH memory.

PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188

controller access.

Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.

After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;

PCMCIA READ stycle is being held in wait state.

After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.

After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto

memory bus to SRAM; host is still held in wait state.

At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.

2. Parameter is not included in production test.

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