STM32MP153C datasheet(171/254 Pages) STMICROELECTRONICS

171 / 254 page

DS12503 Rev 3

171/254

STM32MP153C/F

Electrical characteristics

233

Figure 24. Recommended NRST and NRST_CORE pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST/NRST_CORE pin can go below the VIL(NRST) max level

specified in Table 56. Otherwise the reset is not taken into account by the device.

6.3.19

FMC characteristics

Unless otherwise specified, the parameters given in Table 57 to Table 70 for the FMC

interface are derived from tests performed under the ambient temperature, Fmc_hclk (Fhclk6)

frequency and VDD supply voltage conditions summarized in Table 13: General operating

conditions, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Measurement points are done at CMOS levels: 0.5×VDD

Refer to Section 6.3.17: I/O port characteristics for more details on the input/output

characteristics.

Table 56. NRST and NRST_CORE pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

RPU(2)

Weak pull-up equivalent

resistor(1)

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance must be minimum (~10% order).

VIN = VSS

kΩ

VF(NRST)(2)

2. Guaranteed by design.

NRST/NRST_CORE Input

filtered pulse

1.71 V < VDD < 3.6 V

VNF(NRST)(2)

NRST/NRST_CORE Input

not filtered pulse

1.71 V < VDD < 3.6 V

350

ai14132d

STM32

RPU

NRST(2)

VDD

Filter

Internal Reset

0.1 μF

External

reset circuit (1)

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