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PCI6421 bảng dữ liệu(PDF) 198 Page - Texas Instruments

tên linh kiện PCI6421
Giải thích chi tiết về linh kiện  DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER
PDF  204 Pages
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
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PCI6421 bảng dữ liệu(HTML) 198 Page - Texas Instruments

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10−2
Recommended Operating Conditions (continued)
OPERATION
MIN
NOM
MAX
UNIT
PCI
3.3 V
0.5 VCCP
VCCP
PCI
5 V
2
VCCP
V
High-level input
3.3 V CardBus
0.475 VCC(A/B)
VCC(A/B)
V
VIH†
High-level input
voltage
PC Card
3.3 V 16-bit
2
VCC(A/B)
V
VIH†
voltage
PC Card
5 V 16-bit
2.4
VCC(A/B)
V
PC(0−2)
0.7 VCC
VCC
V
Miscellaneous‡
2
VCC
V
PCI
3.3 V
0
0.3 VCCP
PCI
5 V
0
0.8
V
3.3 V CardBus
0
0.325 VCC(A/B)
V
VIL†
Low-level input voltage
PC Card
3.3 V 16-bit
0
0.8
V
VIL†
Low-level input voltage
PC Card
5 V 16-bit
0
0.8
V
PC(0−2)
0
0.2 VCC
V
Miscellaneous‡
0
0.8
V
PCI
0
VCCP
VI
Input voltage
PC Card
0
VCCCB
V
VI
Input voltage
Miscellaneous‡
0
VCC
V
PCI
0
VCC
VO§
Output voltage
PC Card
0
VCC
V
VO§
Output voltage
Miscellaneous‡
0
VCC
V
tt
Input transition time
PCI and PC Card
1
4
ns
tt
Input transition time
(tr and tf)
Miscellaneous‡
0
6
ns
IO
Output current
TPBIAS outputs
−5.6
1.3
mA
VID
Differential input
Cable inputs during data reception
118
260
mV
VID
Differential input
voltage
Cable inputs during arbitration
168
265
mV
VIC
Common-mode input
TPB cable inputs, source power node
0.4706
2.515
V
VIC
Common-mode input
voltage
TPB cable inputs, nonsource power node
0.4706
2.015¶
V
tPU
Powerup reset time
GRST input
2
ms
S100 operation
±1.08
Receive input jitter
TPA, TPB cable inputs
S200 operation
±0.5
ns
Receive input jitter
TPA, TPB cable inputs
S400 operation
±0.315
ns
Between TPA and TPB
S100 operation
±0.8
Receive input skew
Between TPA and TPB
cable inputs
S200 operation
±0.55
ns
Receive input skew
cable inputs
S400 operation
±0.5
ns
TA
Operating ambient temperature range
0
25
70
°C
TJ#
Virtual junction temperature
0
25
115
°C
† Applies to external inputs and bidirectional buffers without hysteresis
‡ Miscellaneous terminals are 1, 2, 12, 17, 111, 112, 125, 167, 181, and 187 for the PDV packaged device and B10, C09, D01, E03, F12, G03,
H02, L17, P17, and P18 for the GHK packaged device (CNA, SCL, SDA, SUSPEND, GRST, CDx, PHY_TEST_MA, and VSx terminals).
§ Applies to external output buffers
¶ For a node that does not source power, see Section 4.2.2.2 in IEEE Std 1394a−2000.
# These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.



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