PCI6421 datasheet(185/204 Pages) TI

185 / 204 page

9−7

9.9

Smart Card Base Address Register 1−4

Each socket has its own base address register. For example, a device supports three Smart Card sockets uses three

base address registers, BA1 (socket 0), BA2 (socket 1) and BA3 (socket 2).

These registers are used by this function to determine where to forward a memory transaction to the Smart Card

Control and Communication Register sets. Bits 31−12 of this register are read/write and allow the base address to

be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries and the window size is always 4K bytes.

Bits 11−4 are read-only and always return 0s. Write transactions to these bits have no effect. Bit 3 (0b) specifies that

these windows are nonprefetchable. Bits 2−1 (00b) specify that this memory window can allocate anywhere in the

32-bit address space.

Bit

Name

Smart Card base address register 1−4

Type

Default

Bit

Name

Smart Card base address register 1−4

Type

Default

Smart Card base address register 1−4

Offset:

14h, 18h, 1Ch, and 20h

Type:

Read/Write, Read-only

Default:

0000 0000h

9.10 Subsystem Vendor Identification Register

This register is read-update and can be modified through the subsystem vendor ID alias register. Default value is

104Ch. This default value complies with the WLP (Windows Logo Program) requirements without BIOS or EEPROM

configuration. All bits in this register are reset by GRST only.

Bit

Name

Subsystem vendor identification

Type

Default

Subsystem vendor identification

Offset:

2Ch

Type:

Read/Update

Default:

104Ch

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