PCI6421 datasheet(165/204 Pages) TI

165 / 204 page

8−5

8.5

Class Code and Revision ID Register

The class code and revision ID register categorizes the base class, subclass, and programming interface of the

function. The base class is 08h, identifying the controller as a generic system peripheral. The subclass is 05h,

identifying the function as an SD host controller. The programming interface is 01h, indicating that the function is a

standard SD host with DMA capabilities. Furthermore, the TI chip revision is indicated in the least significant byte

(00h). See Table 8−4 for a complete description of the register contents.

Bit

Name

Class code and revision ID

Type

Default

Bit

Name

Class code and revision ID

Type

Default

Class code and revision ID

Offset:

08h

Type:

Read-only

Default:

0805 0XXXh

Table 8−4. Class Code and Revision ID Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31−24

BASECLASS

Base class. This field returns 08h when read, which broadly classifies the function as a generic system

peripheral.

23−16

SUBCLASS

Subclass. This field returns 05h when read, which specifically classifies the function as an SD host

controller.

15−8

PGMIF

Programming interface. If bit 0 (DMA_EN) in the general control register is 0, then this field returns 00h

when read to indicate that the function is a standard SD host without DMA capabilities. If the DMA_EN

bit is 1, then this field returns 01h when read to indicate that the function is a standard SD host with

DMA capabilities.

7−0

CHIPREV

Silicon revision. This field returns the silicon revision of the SD host controller.

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