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STM32L4A6VG bảng dữ liệu(PDF) 239 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 100DMIPS, 1MB Flash, 320KB SRAM, USB OTG FS, audio, AESHASH, ext. SMPS
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STM32L4A6VG bảng dữ liệu(HTML) 239 Page - STMicroelectronics

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STM32L4A6xG
Electrical characteristics
252
Synchronous waveforms and timings
Figure 52 through Figure 55 represent synchronous waveforms and Table 113
through Table 116 provide the corresponding timings. The results shown in these
tables are obtained with the following FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable
•
MemoryType = FMC_MemoryType_CRAM
•
WriteBurst = FMC_WriteBurst_Enable
•
CLKDivision = 1
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period.
1. CL = 30 pF.
2. Guaranteed by characterization results.
Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9THCLK- 1
9THCLK+ 1
ns
tw(NWE)
FMC_NWE low time
7THCLK- 0.5 7THCLK+ 0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
6THCLK+ 2
-
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid
4THCLK- 1
-



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