STM32MP157C datasheet(204/258 Pages) STMICROELECTRONICS

204 / 258 page

Electrical characteristics

STM32MP157C

204/258

DS12505 Rev 2

tSAMP

Sampling time in Sample

and Hold mode

CSH=100nF

(Code transition between

the lowest input code and

the highest input code

when DAC_OUT reaches

final value ± 1LSB)

DACMCR.MODEx[2:0] =

100/101

(BUFFER ON)

-0.7

DACMCR.MODEx[2:0] = 110

(BUFFER OFF)

-11.5

DACMCR.MODEx[2:0] = 111

(INTERNAL BUFFER OFF)

-0.3

CIint

Internal sample and hold

capacitor

2.2

Voffset

Middle code offset for 1

trim code step

VREF+ = 3.6 V

450

µV

VREF+ = 1.8 V

213

IDDA(DAC)

DAC quiescent

consumption from VDDA

DAC output

buffer ON

No load, middle

code (0x800)

-TBD

µA

No load, worst

code (0xF1C)

-TBD

DAC output

buffer OFF

No load,

middle/worst

code (0x800)

-TBD

Sample and Hold mode,

CSH = 100 nF

-TBD

IDDV(DAC)

DAC consumption from

VREF+

DAC output

buffer ON

No load, middle

code (0x800)

-TBD

No load, worst

code (0xF1C)

-TBD

DAC output

buffer OFF

No load,

middle/worst

code (0x800)

-TBD

Sample and Hold mode, Buffer

ON, CSH = 100 nF (worst code)

-TBD

Sample and Hold mode, Buffer

OFF, CSH = 100 nF (worst code)

-TBD

1. Guaranteed by design.

2. Since VREF+ must always be ≤ VDDA, maximum VDAC_OUT = minimum value between Max(VREF+) and Max(VDDA-0.2)

3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).

Table 80. DAC characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 81. DAC accuracy

Symbol

Parameter

Conditions

Min

Typ(1)

Max

Unit

DNL

Differential

non

linearity(2)

DAC output buffer ON

±2

TBD

LSB

DAC output buffer OFF

±2

TBD

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