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STR720 - S-D ANALOG/DIGITAL CONVERTER (ADC)

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22.3.5

Clock Timing

The sigma-delta modulator must run at a clock frequency (F

Mod, oversampling rate) not

greater than 4 MHz. The registers in this converter are clocked by the APB clock. Double

clocked synchronization for data crossing clock boundaries avoids any metastability issue. It

is up to the user to correctly program the prescaler, to generate the correct oversampling

frequency based on the APB frequency:

where:

Presc = Value written in prescaler register (ADCCPR)

fAPB = APB bus clock frequency

= sampling frequency

In case the low-rate operation mode is selected, the formula above becomes:

As an example, if APB clock frequency is 33 MHz and required sampling frequency is 100 Hz,

ADCCPR register should be configured by writing 80 into it using the normal decimation

mode. The same prescaler value, using low-rate decimation mode, would produce a sampling

rate of 10 Hz.

Note

If the prescaler is set to generate a sampling frequency greater than specified,

conversion performance is not guaranteed.

22.3.6

Σ−∆ Modulator

The

Σ−∆ modulator used is a single-bit design, second-order feedback architecture modulator

including two integrators, two summing junctions and a comparator. The gains m1–m4 are set

by capacitor ratios in the integrators.

Figure 57. Modulator architecture

Presc

fAPB

Fs 512 8

⋅⋅

---------------------------

Presc

fAPB

Fs 5120 8

⋅⋅

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