STR720 datasheet(319/401 Pages) STMICROELECTRONICS

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STR720 - EXTENDED FUNCTION TIMER (EFT)

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Then, on a valid event on the ICAPA pin, the counter is initialized to FFFCh and OLVLB bit is

loaded on the OCMPA pin after four clock period. When the value of the counter is equal to the

value of the contents of the OCAR register, the OLVLA bit is output on the OCMPA pin (See

Figure 52).

Note

– The OCFA bit cannot be set by hardware in one pulse mode but the OCFB bit can generate

an Output Compare interrupt.

– The ICFA bit is set when an active edge occurs and can generate an interrupt if the ICAIE

bit is set. The ICAR register will have the value FFFCh.

– When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set with

FOLVA= 1, the OPM mode is the only active one, otherwise the PWM mode is the only active

one.

– Forced Compare B mode works in OPM

– Input Capture B function works in OPM

– When OCAR = FFFBh in OPM, then a pulse of width FFFFh is generated

– If event occurs on ICAPA again before the Counter reaches the value of OCAR, then the

Counter will be reset again and the pulse generated might be longer than expected as in

Figure 52.

– If a write operation is performed on the counter register before the Counter reaches the value

of OCAR, then the Counter will be reset again and the pulse generated might be longer than

expected.

– If a write operation is performed on the counter register after the Counter reaches the value

of OCAR, then there will have no effect on the waveform.

Figure 51. One Pulse Mode Cycle

event occurs

Counter is

initialized

to FFFCh

OCMPA = OLVLB

Counter

= OCAR

OCMPA = OLVLA

When

on ICAPA

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