STR720 datasheet(291/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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19.6.2

Endpoint-Specific Registers

The number of these registers varies according to the number of endpoints that the USB

Peripheral is designed to handle. The USB Peripheral supports up to 8 endpoints. Each USB

device must support a control endpoint whose address (EA bits) must be set to 0. The USB

Peripheral behaves in an undefined way if multiple endpoints are enabled having the same

endpoint number value. For each endpoint, an USB_EPnR register is available to store the

endpoint specific information.

USB Endpoint n Register (USB_EPnR)

Address Offset: 00h to 2Ch

Reset value: 0000 0000 0000 0000b (0000h)

They are also reset when an USB reset is received from the USB bus or forced through bit

FRES in the CTLR register, except the CTR_RX and CTR_TX bits, which are kept unchanged

to avoid missing a correct packet notification immediately followed by an USB reset event.

Each endpoint has its USB_EPnR register where n is the endpoint identifier.

Read-modify-write cycles on these registers should be avoided because between the read

and the write operations some bits could be set by the hardware and the next write would

modify them before the microprocessor has the time to detect the change. For this purpose,

all bits affected by this problem have an ‘invariant’ value that must be used whenever their

modification is not required. It is recommended to modify these registers with a load

instruction where all the bits, which can be modified only by the hardware, are written with

their ‘invariant’ value.

765

STAT

RX[1:0]

TYPE[1:0]

STAT

TX[1:0]

EA[3:0]

r-c

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