STR720 datasheet(284/401 Pages) STMICROELECTRONICS

284 / 401 page

STR720 - USB SLAVE INTERFACE (USB)

284/401

Only the bits related to events, which are serviced, are cleared. At the end of the service

routine, another interrupt will be requested, to service the remaining conditions.

To avoid spurious clearing of some bits, it is recommended to clear them with a load

instruction where all bits which must not be altered are written with 1, and all bits to be cleared

are written with ‘0’ (these bits can only be cleared by software). Read-modify-write cycles

should be avoided because between the read and the write operations another bit could be

set by the hardware and the next write will clear it before the microprocessor has the time to

serve the event.

The following describes each bit in detail:

Bit 15

CTR: Correct Transfer

This bit is set by the hardware to indicate that an endpoint has successfully

completed a transaction; using DIR and EP_ID bits software can determine

which endpoint requested the interrupt. This bit is read-only.

Bit 14

DOVR: DMA over / underrun

This bit is set if the microcontroller has not been able to respond in time to an

USB memory request. The USB Peripheral handles this event in the following

way: During reception an ACK handshake packet is not sent, during

transmission a bit-stuff error is forced on the transmitted stream; in both cases

the host will retry the transaction. The DOVR interrupt should never occur

during normal operations. Since the failed transaction is retried by the host, the

application software has the chance to speed-up device operations during this

interrupt handling, to be ready for the next transaction retry; however this does

not happen during Isochronous transfers (no isochronous transaction is anyway

retried) leading to a loss of data in this case. This bit is read/write but only ‘0’

can be written and writing ‘1’ has no effect.

STR720 bảng dữ liệu(PDF) 284 Page - STMicroelectronics