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STR720 bảng dữ liệu(PDF) 220 Page - STMicroelectronics |
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STR720 bảng dữ liệu(HTML) 220 Page - STMicroelectronics |
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220 / 401 page  STR720 - CONTROLLER AREA NETWORK (CAN) 220/401 IFn Command Request Registers (CAN_IFn_CRR) Address offset: 20h (CAN_IF1_CRR), 80h (CAN_IF2_CRR) Reset Value: 0001h A message transfer is started as soon as the application software has written the message number to the Command Request Register. With this write operation, the Busy bit is automatically set to notify the CPU that a transfer is in progress. After a waiting time of 3 to 6 APB_CLK periods, the transfer between the Interface Register and the Message RAM is completed. The Busy bit is cleared. Note When a Message Number that is not valid is written into the Command Request Register, the Message Number will be transformed into a valid value and that Message Object will be transferred. 15 14 13 12 11 10 9876 5 4 3 2 1 0 Busy Reserved Message Number r rw Bit 15 Busy: Busy Flag 0: Read/write action has finished. 1: Writing to the IFn Command Request Register is in progress. This bit can only be read by the software. Bits 14:6 Reserved These are reserved bits. These bits are always read as ‘0’ and must always be written with ‘0’. Bits 5:0 Message Number 0x01-0x20: Valid Message Number, the Message Object in the Message RAM is selected for data transfer. 0x00: Not a valid Message Number, interpreted as 0x20. 0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. 1 |
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