AR8327-AL1A-R datasheet(152/394 Pages) ETC2

152 / 394 page

152 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

152 • June 2011

COMPANY CONFIDENTIAL

Table 3-134.

Port 2 Priority Control Register

3.6.29

PORT2_LEARN_LIMIT

Address 0x0680

SFT&HW RST

Table 3-135 summarizes the PORT2_LEARN_LIMIT Register

Table 3-135.

Port 2 Learn Limit Control Register

Bit

R/W

Inital

Value

Mnemonic

Description

31:21

R/O

RESERVED

R/W

EG_MAC_BASE_VLAN_EN_2

R/O

RESERVED

R/W

DA_PRI_EN_2

1'b1: DA priority can be used for QOS.

R/W

VLAN_PRI_EN_2

1'b1: VLAN priority can be used for

QOS.

R/W

IP_PRI_EN_2

1'b1: TOS/TC can be used for QOS.

15:8

R/O

RESERVED

7:6

R/W

DA_PRI_SEL_2

DA priority selected level for QOS.

There are five levels priority for QOS.

The highest is priority in packet

header.

The others are selected by these bits. If

these bits are set to zero, DA priority is

selected after header. If these bits are

set to n, DA priority is selected after the

priority set to n-1.

5:4

R/W

VLAN_PRI_SEL_2

DA priority selected level for QOS.

3:2

R/W

IP_PRI_SEL_2

IP priority selected level for QOS.

1:0

R/O

RESERVED

Bit

R/W

Inital

Value

Mnemonic

Description

31:28

R/O

RESERVED

R/W

IGMP_LEARN_LIMIT_EN_2

1'b1: IGMP Learn Limit enable.

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