AR8327-AL1A-R datasheet(101/394 Pages) ETC2

101 / 394 page

Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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101

3.4.6

WIN_RULE_CTRL0

Address 0x0218

SFT&HW RST

Table 3-66 summarizes the WIN_RULE_CTRL0 Register 0

Table 3-66.

Window Rule Control Register 0

3.4.7

WIN_RULE_CTRL1

Address 0x021C

SFT&HW RST

Table 3-67 summarizes the WIN_RULE_CTRL1 Register 1

R/W

DHCP_EN_4

1'b1: acknowledge DHCP frame enable

1'b0: don't acknowledge DHCP frame

R/O

EAPOL_EN_4

1'b1: hardware acknowledge 802.1x frame, and

send frame copy or redirect to cpu controlled by

"EAPAL_REDIRECT_EN"

R/W

IGMP_LEAVE_EN_4

1'b1: enable IGMP/MLD hardware fast leave.

R/W

IGMP_JOIN_EN_4

1'b1: enable IGMP/MLD hardware join.

R/W

IGMP_MLD_EN_4

IGMP/MLD snooping enable. If this bit is set to

1'b1, the port will examine all received frames

and copy or redirect to cpu port controlled by

IGMP_COPY_EN.

Bit

R/W

Inital

Value

Mnemonic

Description

Bit

R/W

Inital

Value

Mnemonic

Description

31:28

R/O

RESERVED

27:24

R/W

L4_LENGTH_0

These bit indicate that window rule in port0 to

select length of L4, from L4_OFFSET_0.

23:20

R/W

L3_LENGTH_0

These bit indicate that window rule in port0 to

select length of L3, from L3_OFFSET_0.

19:16

R/W

L2_LENGTH_0

These bit indicate that window rule in port0 to

select length of L2, from L2_OFFSET_0.

R/W

RESERVED

14:10

R/W

L4_OFFSET_0

These bit indicate that window rule in port0 to

select offset of L3, from TCP/UDP header.

9:5

R/W

L3_OFFSET_0

These bit indicate that window rule in port0 to

select offset of L3, from IP header.

4:0

R/W

L2_OFFSET_0

These bit indicate that window rule in port0 to

select offset of L2, from MAC DA.

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