PIC18F4520ESLASHMLQTP datasheet(361/390 Pages) MICROCHIP

361 / 390 page

 2004 Microchip Technology Inc.

Preliminary

DS39631A-page 359

PIC18F2420/2520/4420/4520

FIGURE 26-22:

A/D CONVERSION TIMING

TABLE 26-25: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

Note

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . .

TCY

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

130

TAD

A/D Clock Period

PIC18FXXXX

0.7

25.0(1)

µsTOSC based, VREF ≥ 3.0V

PIC18LFXXXX

1.4

25.0(1)

µsVDD = 2.0V;

TOSC based, VREF full range

PIC18FXXXX

TBD

µs

A/D RC mode

PIC18LFXXXX

TBD

µsVDD = 2.0V; A/D RC mode

131

TCNV

Conversion Time

(not including acquisition time) (Note 2)

TAD

132

TACQ

Acquisition Time (Note 3)

1.4

TBD

—

µs

-40

°C to +85°C

°C ≤ to ≤ +85°C

135

TSWC

Switching Time from Convert

→ Sample

—

(Note 4)

TBD

TDIS

Discharge Time

0.2

—

µs

Legend: TBD = To Be Determined

Note 1:

The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

ADRES register may be read on the following TCY cycle.

The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50

Ω.

On the following cycle of the device clock.

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