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PIC16F818-E/ML bảng dữ liệu(PDF) 134 Page - Microchip Technology |
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PIC16F818-E/ML bảng dữ liệu(HTML) 134 Page - Microchip Technology |
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134 / 176 page  PIC16F818/819 DS39598E-page 132 2004 Microchip Technology Inc. FIGURE 15-5: CLKO AND I/O TIMING TABLE 15-2: CLKO AND I/O TIMING REQUIREMENTS Note: Refer to Figure 15-3 for load conditions. OSC1 CLKO I/O pin (Input) I/O pin (Output) Q4 Q1 Q2 Q3 10 13 14 17 20, 21 19 18 15 11 12 16 Old Value New Value Param No. Symbol Characteristic Min Typ† Max Units Conditions 10* TOSH2CKLOSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11* TOSH2CKHOSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) 12* TCKR CLKO Rise Time — 35 100 ns (Note 1) 13* TCKF CLKO Fall Time — 35 100 ns (Note 1) 14* TCKL2IOVCLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15* TIOV2CKH Port In Valid before CLKO ↑ TOSC + 200 — — ns (Note 1) 16* TCKH2IOI Port In Hold after CLKO ↑ 0— — ns (Note 1) 17* TOSH2IOVOSC1 ↑ (Q1 cycle) to Port Out Valid — 100 255 ns 18* TOSH2IOIOSC1 ↑ (Q2 cycle) to Port Input Invalid (I/O in hold time) PIC16F818/819 100 — — ns PIC16LF818/819 200 — — ns 19* TIOV2OSH Port Input Valid to OSC1 ↑ (I/O in setup time) 0 — — ns 20* TIOR Port Output Rise Time PIC16F818/819 — 10 40 ns PIC16LF818/819 — — 145 ns 21* TIOF Port Output Fall Time PIC16F818/819 — 10 40 ns PIC16LF818/819 — — 145 ns 22††* TINP INT pin High or Low Time TCY —— ns 23††* TRBP RB7:RB4 Change INT High or Low Time TCY —— ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. |
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