AN701 / Vishay Siliconix - bảng dữ liệu(PDF) Chat AI

AN701 Datasheet with Chat AI

Hello, Please ask a question about AN701 Datasheet

# Example questions: ➢ What range of capacitance is suggested for electrolytic and ceramic capacitors, and what are their respective roles?
➢ What is the difference in delay times between the current mode comparator and the peak current limiting comparator, and why is this difference important?
➢ What is the primary purpose of the leading-edge blanking/suppression feature in the si9114a?

Part No.	AN701
Manufacturer	VISHAY
Size	1Mb
Pages	19 pages
Description	Designing High-Frequency DC-to-DC Converters With the Si9114A Switchmode Controller

Datasheet Summary with AI

# Si9114A Switchmode Controller

## Overview
The Si9114A is a monolithic switchmode PWM controller designed for high-frequency DC-to-DC converters (up to 1 MHz). It builds upon the Si9100, offering reduced delay times and added features for efficient, low-power conversion. Utilizes constant frequency current mode control.

## Key Features
· High-frequency operation (up to 1 MHz)
· Constant frequency current mode control
· Integrated power MOSFET
· High-voltage start circuitry
· Low power consumption
· 50% duty cycle limitation for core reset avoidance
· Cycle-by-cycle current limit protection
· Fast transient response
· Automatic input voltage feed-forward compensation
· Shutdown pin for fast, latched termination
· Soft-start functionality to reduce component stress
· Oscillator synchronization capability

## Startup Circuit
· Uses a depletion mode MOSFET for startup, avoiding large capacitors.
· Operates initially with the depletion transistor on, charging VCC to 9.2V.
· Transformer provides power to VCC once it reaches 9.2V, turning off the depletion MOSFET.

## Shutdown
· Fast latched shutdown (300ns delay).
· Can be reset via UVLO or by momentarily dropping VCC below the UVLO threshold.
· Includes internal pull-up resistor on the shutdown pin.

## Reference Voltage
· Buffered band gap type, sourcing up to 5mA.
· Requires external decoupling (100nF ceramic or small tantalum).

## Error Amplifier
· PMOS input, folded cascade gain stage.
· 77dB open loop gain, 2.7 MHz unity gain bandwidth.
· Requires a 100pF bypass capacitor from NINV to Comp.

## Soft-Start
· Clamps the error amplifier output, charging an external capacitor (CSS) linearly to 4.6V.
· Reduces inrush current and component stress.

## Oscillator
· External timing components (RT, CT) set the frequency.
· Includes divide-by-two circuitry.
· SYNC pin allows for external clock synchronization.

## Current Sense
· Uses current mode control with scaled inductor current sampling.
· Requires careful filtering to eliminate spikes and noise.
· Built-in leading-edge blanking/suppression.

## Power Supply Considerations
· Requires well-decoupled power supply pins (VCC, -VIN).
· Electrolytic and ceramic capacitors recommended for decoupling.
· Gate drive requirements for the power MOSFET should be considered.