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Part No.	US2005L-AG6-R
Manufacturer	UTC
Size	165 Kbytes
Pages	5 pages
Description	FIXED CURRENT LIMIT POWER DISTRIBUTION SWITCH

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# US2005 Fixed Current Limit Power Distribution Switch

## Description
️· UTC US2005 is a low-voltage, cost-effective high-side power switch with current limiting.
️· Suitable for power distribution/control in DTVs, printers, STBs, PCs, PDAs, and peripherals.
️· Features charge pump, soft-start, thermal shutdown, UVLO, fault flag output, and low quiescent current (80μA).
️· Allows momentary high current surges and output slew rate control via external capacitor.

## Features
️· Built-in 80mΩ N-MOSFET.
️· Open-drain fault flag output.
️· Input voltage: 2.5V to 5.5V.
️· Quiescent current: 80μA.
️· Current limit options: 0.5A, 0.8A, 1.2A.
️· Automatic-on output after fault.
️· Thermal protection.
️· Under-voltage lock-out (UVLO).

## Ordering Information
️· US2005L-AG6-R / US2005G-AG6-R: SOT-26 package, Tape Reel.

## Pin Description
️· PIN 1 (IN): Supply input.
️· PIN 2 (GND): Ground.
️· PIN 3 (EN): Enable input (active-high/low).
️· PIN 4 (FLG): Fault status output (open-drain, low indicates fault).
️· PIN 5 (CSLEW): Slew rate control (uses external capacitor).
️· PIN 6 (OUT): Switch output.

## Absolute Maximum Ratings (TA=25°C)
️· Supply Voltage (VIN): 6V
️· Enable Input Voltage (VEN): 5.5V
️· Power Dissipation (PD): 0.4W
️· Junction Temperature (TJ): 150°C
️· Storage Temperature (TSTG): -65 to 150°C

## Thermal Data
️· Package Thermal Resistance (θJA): 230°C/W

## Recommended Operating Conditions
️· Supply Input Voltage (VIN): 2.5V to 5.5V
️· Enable Input Voltage (VI(EN)): 0 to 5.5V
️· Continuous Output Current: 0 to 2.1A
️· Ambient Temperature (TA): -40 to +85°C

## Electrical Characteristics (VIN=5V, TAMBIENT=25°C)
️· RDS(ON): 70-125 mΩ @ 100mA
️· Current Limits: 0.5A, 0.8A, 1.2A (selectable).
️· UVLO Threshold (Rising): 2.0-2.25V
️· UVLO Threshold (Falling): 1.9-2.15V
️· Fault Output Voltage (VFAULT): 0.25-0.4V @ 10mA

## AC Characteristics
️· Output Turn-ON Rise Time (tRISE): 500-1500 μs
️· Output Turn-ON Delay (tON_DLY): 1000-1500 μs
️· Output Turn-OFF Delay (tOFF_DLY): 700 μs
️· Delay Before Asserting FLG (tD_FAULT): 20-49ms